Cache Coherency, UVM and TLM related, SV concepts, Past projects.
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
A function that calculates the number of bits turned on on a certain number
Diferencia entre latchs y flip-flops Proyectos destacables de la universidad ¿Como le bajarias la corriente al circuito para que no gaste mucho voltaje?, entre muchas mas.
Create a fifo and test it.
Memory Consistency
MOSEI protocol. Cache hierarchy.
Design clock gating in system verilog. Difference between verilog and system verilog.
setup/hold time ;verification coverages and types
Q1. FIFO depth, given read and write rates for a burst of x writes Q2. a=0; b=0; c=1; #1 a=c; #1 b =a; (Give waveforms) Q3. a<=0; b<=0; c<=1; #1 a<=c; #1 b< =a; (Give waveforms) Q4. a=0; b=0; c=1; a= #1 c; b=#1 a; (Give waveforms) Q5. a<=0; b<=0; c<=1; a<= #1 c; b<=#1 a; (Give waveforms) Q6. You have incoming bit stream. You can't store them. You get a new bit at every clock edge, find modulo 5 of the updated number everytime. Eg, if bitstream is 10111, you find modulo of 1, then 10, then 101 and so on..
Describes one of your projects
Viewing 2101 - 2110 interview questions