Sv and UVM project knowledge protocol mentioned in CV
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
FSM, SystermVerilog, and software leetcode related questions.
Q. Describe your test plan for a FIFO
write HDL code for a FSM
Linux: how to create a file, how to find all file that contain FOO, with case sensitive and case insensitive.
evaluation regions semaphore virtual interfaces modport uvm
1. UVM Methodology
How does polymorphism work in practice in OOP? How is it implemented?
given an array of N integers and int k find out if there are 3 numbers that together sum up to k
Computer Architecture. OOPs. System Verilog and UVM. Graphics Architecture .
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