Digital electronics, Verilog, System Verilog, UVM
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Constraints, p_sequencer, m_sequencer, tb flow, agent
Explain about your projects and major responsibilities handled?
set up time, hold time
Describe your previous work experience
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
I was asked about basic C++ knowledge, such as encapsulation and polymorphism. I was also asked to interpret some assembly code. A design manager asked me conceptual questions about computer systems and architecture, such as cache and virtual memory.
Verilog questions and digital circuit designs
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
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