State machines, VHDL, basic logic and design.
Verification Engineer Interview Questions
2,559 verification engineer interview questions shared by candidates
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Technical Screening: Q: I was asked about basic programming questions like Leet Code (easy) but mostly based on array, hash-maps, strings and also resume discussion Full-Panel: Q: SystemVerilog constraints, fork-join, mailbox and semaphores based questions Q: Was asked to write scoreboard for a Asynchronous FIFO Q: Monitor and scoreboard code for an AXI write transaction (project based) Q: Resume based discussions Q: Some basic programming problems in language of preference
What is setup and hold time What is skew What is synchronous and asynchronous reset
Design a FSM to detect a certain sequence of numbers.
1. Programming questions like Fibonacci series. 2. Some questions related to Perl Programming. 3. Some questions on state machine design. 4. Synthesizable and non synthesizable constructs in Verilog. 5. Be thorough with the stuff on the resume.
digital, sv, uvm, verilog, scripting basics
set up time, hold time
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
I was asked about basic C++ knowledge, such as encapsulation and polymorphism. I was also asked to interpret some assembly code. A design manager asked me conceptual questions about computer systems and architecture, such as cache and virtual memory.
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