Explain pg gate sims, few upf concepts
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Asyn FIFO and UVM detail Like YOU HAVE TO CODING IT.
The first question was to make from mix the function f=(abc’)’. After this I was asked to build a 4 to 1 mux from 2to1 muxes. Then I was asked about registers and they wanted me to build a FIFO.
Given Axi related specification and asked me to ask the questions related to specification.
implement sort array, in your way
Review resume, things you have done, technology you work with, UVM,
Tell me about your self. Come up with a test case for a specific user need
1. They asked me to explain a flip flop function with wave forms and an rtl programme in Verilog. 2. I was given a sequence of input waveform and was asked to design a state diagram and also to write an rtl code in Verilog 3. Functionalities of the Universal gates, clocking domains, STA, few analogue questions 4. To explain the previously done projects of my academic qualification in detail
For a six-deep FIFO with one (and two clocks), push and pop operations, what specific test cases will you use to verify the design?
ram,rom,hard disc,multiplier code in 8085,sta,maximum frequency
Viewing 761 - 770 interview questions