Various Verilog detailed questions. I had about 3 months experience of Verilog some 8 years ago. I can't remember the details of the questions.
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
1. The interview showed a complex SVA and asked me to explain the functionality of the assertion. 2. A C function which reads the value from a specific address. 3. A question about Functional coverage 4. Questions about coverage (code and functional) 5. UVM factory, config_db, 6. Formal verification 7. Processor based verification. Basically they were asking how you verify a Subsystem using C/C++ 8. AHB-AXI bus
Interview process had 5 technical rounds including question on puzzles , mathematical derivation related logic, permutation and combination questions mostly , logical questions to derive at particular answer. 1. get 4 ltr out of 3 ltr and 5 ltr jar 2. combination question 3. few question relating to infrastructure as code
Asked about design project experience.
SV and UVM related questions and ur understanding
what value the interviewee could supply to the company?
If you had to add cache in the pipeline stage, where would you add it?
Usage of trees
Why you want to join volvo
Questions ranged from logic gates, computer architecture (pipelining ooo), verification and software (data structures)
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