How would you approach this problem?
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Show your verification plan with this design
what is your verification process?
At first, they ask me about my previous experience and started to ask question about it. Then it became technical. Some question about gain, impedance, noise, bandwidth, transient response (under switching events) in common circuit topologies. What strategy would I use to face PVT variations on a circuit. Definition of Phase noise and Jitter and some questions about the advantages of flash architecture in ADC.
Explain the UVM Sequencer driver communication
logic gates rc network cmos basics operation regions vi characteristics diodes fet
what did u understand about this Role?
UVM Phases, why do we use Virtual, Constraints , Use of randc , assertions , how do you override , how do you analyze verification metrics, callbacks
Blocking vs non blocking in Verilog and Logic Design. Pipelining concept. Basic algorithms, time/space complexity. Virtual functions in C++
Online interview: 1. What is polymorphism ? 2. Design a 3 bit shift register in verilog RTL ? 3. For a FIFO design, what kind of assertions will you write(what conditions would you check for proper functioning of the FIFO) ?
Viewing 871 - 880 interview questions