Write a test plan for asynchronous reset flip flop
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
introduce yourself and why you want to work at apple
Design, Test plan, SystemVerilog ......
- More details about projects and experiences on the resume - 3 questions DSA related to embedded systems (only walking through ideas)
Questions on writing constraints for the given sequence.
We want to send a specific amount of data and to prevent errors, we want to divide the data into several segments randomly within a certain size range. How can we perform this division so that there will definitely be enough data for all the remaining packets?
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
Had to write a verilog code for some handshaking protocol.
Digital questions, UVM environment based questions
Implement a circuit board the receives an 8-bit bus. The output is an 8-bit bus where the first net that is '1' in the input is also '1' in the output, the rest are '0' (in other words - "find first '1' in the input bus).
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