- timing questions: setup, hold, slack, critical path, max frequency, what is STA, how to improve the timing, etc
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
Q: Number of test vectors for a priority encoder with "n" inputs.
Q: FSM for detecting a particular sequence.
Deep copy vs shallow copy in systemVerilog
What is coherency, consistency, difference. How do you ensure them, protocols, practices. How do you verify them (project related stuff). Questions on UVM, SystemVerilog and Verilog
SV UVM knowledge DV knowledge Qs on RTL GLS IP specific questions background and asking to debug a piece of code
why do we need factory registration in UVM testbench
OSI model Protocols in network layers Basic OS,DBMS,Java questions Questions based on Resume
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Difference between logic and reg? Difference between static casting and dynamic casting? resouce db and its significance? What is throughput rate? event scheduler in SV? UVM objections? Driver sequence handshake?
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