1: what is set up and hold time?
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
About the skills I have and how that they could use that
I don't see the point of listing a position for over 70 days and giving no response to people, at least those whose names are not Andersson or Svensson.
all about system verilog and uvm
Coding of driver and clock generation
what are basic logic gates? design and gate using mux?
Mostly on the work you did
From where did I completed my education
1).Questions on array methods. 2).Asked to write scoreboard code in general. 3).Questions on TLM ports.
1. Verification process 2. Test plan 3. UVM and System verilog - logic, coding questions, UVM_Info
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