Design an FSM and write Verilog code for an asynchronous fifo
Verification Interview Questions
3,655 verification interview questions shared by candidates
They asked about mu uvm design verification project
Was tested on computer architecture, pipeline, hazards, fsm, uvm basics, writing system verilog test benches for resume projects
Random number generations, assertions, constraints etc.
It was strange interview I ever had. It was a telephonic interview and he asked me to explain system verilog code for small program, he was writing program as I was explaining him and he expect program to compile and run. Its all telephonic. which is strange. I did not like it and also not selected for next round
UVM TB questions, sequence, sequencer and driver protocol, SV randomization questions
pipeline processor architecture, hazard, shared memory problem, cache issues—remote repeated words both in SystemVerilog. I answered how to do it in python, but he insisted Con using c or SystemVerilog. In the last question, he asked me why I choose design verification. The whole procedure lasts about 53 minutes, quite tense I would say. I did not answer the memory coherence and delete repeat words in C. I would say I did not do it well. Hoping this could help others to get job. Just preparing questions.
Memory allocation
Create a presentation on your past projects.
Self-assessment, technical skills and soft skills
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