Asked about clock domain crossing, asynchronous clocks, and difference between sequential and combinational logic.
Verification Interview Questions
3,655 verification interview questions shared by candidates
Scripting and programming interview was about file parsing and automation (Analyse the code, find the error, correct it) General keep an eye on digital design concepts like FSMs, Clock and Timing, CDC, etc.
Questions were from Digital electronics and other subjects
1. Basics of system verilog and uvm ll be asked, 2. description of project worked on 3. Bugs found and issuedls faced
Explain the structure of uvm verification environment.
Basic SV, UVM, Verilog, Verification flow etch
Can a modport include a clocking block, give an example of both.
FIFO, LIFO in Verilog
Why should i be hiered?
It gets very technical ranging from Electrical fundamentals to RF fundamentals and then they start to dig deep on each aspect. Know your chip caps really well! I was asked questions on smith charts, imedance matching, typical RF receiver/transmitter systems, signal integrity issues, characteristics of RF amps. As far as behavioral questions were concerned - challenges faced in your last project, how did u solve it and what would your ex boss say about you if I asked him for a reference.
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