Can you explain common centroid layout?
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
The skype interview was too technical and to ASIC-oriented. I work for 4 years. At the end of University I could answer it, now I forgot a lot...
Walk through past designs, clock crossings, some scenarios just the usual but nothing that was out of line for the position
Asked basics
reorder buffer store pointer.
1.How to deal with multi-bit CDC 2.How to analysis timing for clock gating cell 3.Synthesis flow
Just for asking ASIC knowledge.
How to build a synchronizer for one bit, for multiple bits and for clock domains that run at different frequencies? How to do truncate and the sign extension in arithmetic operation (at first I did not catch the point, and the interviewer guide me to the right answer)?
All the questions are very straightforward, like the definitions of setup time and hold time, and how to avoid setup and hold time violation.
What is the difference between the syn and asyn FIFO? Is there any way for cross domain signal transfer? Tell me related technique and writing verilog code to describe it.
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