mostly regular
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Describe the 5 stages in MIPS pipeline structure.
fifo design
The phone screen with basic questions like your visa status.
Bus protocols like SPI, ARM etc
Low power design, STA
STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
The second was about state machine, how to output true for every two consecutive 1s.
Difference Between Associative array and Dynamic Arrya
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