What was my most challenging project? And how would I verify the correct functionality of it?
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Was asked about basic protocols for PCIE. Basic questions on CDC. Types of violations that the CDC tools complain - eg: no_sync, combi logic before double sync, multi bit double syncing, re-convergence etc. Code async reset FF and sync reset FF. What are the dis/advantages of one over the other.
Lots of questions about pmos and nmos (how to build nand gates, inverters), etc, how a pll works, how different things affect the output, transmission lines (parasitics, series vs parallel etc), flip flops, latches, op amps (designing lots of different op amps and discussing their rules)
Could you please explain FIFO to me?
Explain the UVM Sequencer driver communication
the journey and background till that moment.
Why do you want to join Synopsys?
Design FIFO module control for synchronous write and asynchronous read with given constraints (full, empty, etc)
Clock Domain Crossing , RTL Design Constructs using Verilog , System Verilog and VHDL , Constraints in SDC, SDGC for spyglass
Pros and cons of vernier TDC
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