cross clock domain questions
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
asynchronous clock domain crossing, FIFO pointer logic, timing constraints, a divide by 3 clock generator
Where do you see yourself in 5-10 years?
Some cutting square questions,
Problem on timing analysis
Decimal to gray function with logic gates
Setup/hold validation calculate, FSM design questions
Text book based questions. Really boring
clock tree synthesis
This was a friendly interview to know my aspirations and skill sets.. They asked on my domain experiences, why I choose Ericsson and my expectations from the company
Viewing 321 - 330 interview questions