Explain Setup and hold for a latch.
Asic Design Engineer Interview Questions
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Design a FIFO hardware
False paths and Multiple cycle path examples.
Personal research, DVFS, CDC, metastable, asynchronous FIFO, synchronizer, level shifter, clock gating, power gating, dynamic power, leakage power.
all about resume, STA, DFT, Pipelining
There were no out of the box questions.
calculate set up , hold in terms of some 10 parameters.
Why you do clk gating in your design
How to determine which register you want to gate in netlist ?
How often do you use the digital programming software?
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