CMOS characteristics?
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
c++ swap, pipeline
Constraint randomization based question linking to AXI and memory filling
Two questions： 1. 2 2bits comparators to 4 bits comparators, and reduce the delay to 1 units 1. data buffer like 0100000001, most simple rtl design to get the length (which is 9)
design sensor with minimal logic block
Write a Fibonacci number generator in Verilog, output a number in each cycle.
Current project architecture and role. SV and UVM related. SV constraint, coverage, assertions. UVM architecture and flow. Verification strategy related.
Digital Design basics
explain about cache
What is a fpga and what is a lookup table?
Viewing 571 - 580 interview questions