Why do we need a virtual interface?
Verification Engineer Interview Questions
2,564 verification engineer interview questions shared by candidates
How do you determine if these two circuits (shown in a slide) are equivalent?
There was no tehnical interview for no experience engineer
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
Asked about Basic Signalling like Block Section Working, Logic Circuits, Control Table Checking, Signalling Plan, CBTC Principles, Automation in C#, Process Automation & outcome. Success Ratio & feasibility of Automation in Signalling
Based in UVM and System verilog and project related questions
technical questions which are related to projects you have done
c++ basics - virtual functions, function vs task difference, coverage , constraints
write assertions for the given timing diagram
program for ring counter and Johnson counter in verilog
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