Timing closure. How noise(cross-talk) affect setup/hold? How metal dimension affect timing?
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
Write verilog code for implementing a NAND gate using a MUX
Write a uvm driver for a simple valid-ready protocol. - When data is available assert the valid - Keep the data stable and valid high until ready is asserted - De-assert the valid once ready is asserted interface if input clk; logic [15:0] Data; logic Valid; logic Ready; endinterface
Design basic state machines (mealy moore) and give the circuit implementation
what's the logic of a mux
Design a state machine to implement back face culling of polygons in a simple graphics renderer.
If you had a risc instruction set architecture with a 4 bit ASLU unit, how would you extend your architecture to include an 8 or 16 bit ALSU unit without heavily modifying the hardware?
The rest were general knowledge: clock domain crossings, cashe, power reduction.
No difficult question
Some computer architecture questions like pipeline design and pipeline hazards
Viewing 341 - 350 interview questions