Lots of questions about RTL design. Hard to remember every single one. But it's really difficult.
Asic Design Engineer Interview Questions
710 asic design engineer interview questions shared by candidates
What is setup and hold time?
Asked to walk through the design process of an arbiter module with certain specifications.
How do you understand leakage?
Static timing analysis and Clock domain crossing
Python question and verilog question to implement the same thing
introduce your last position/ project?
One of the questions is about clock divider and the interviewer asked a lot different questions related to divider design
basic concept of pipeline state machine of sequence detector C program of a function about pattern replace
Out of Order Processors, Standard Pipeline Description, Cache Memory Design, State Machine Design
Viewing 351 - 360 interview questions